The present invention generally relates to a communication system to provide efficient communication between a microprocessor and an external device over a serial bus. The present invention still more particularly relates to such a system which is implemented in integrated circuit form and wherein, through a new and improved register access message and system architecture, register reads and writes, error messages, and interrupt messages can be conducted between the microprocessor and the external device in an expedited manner over the serial bus. The communication system of the present invention disclosed herein is incorporated into a hands-free, multiple feature telephone unit adapted for use in an Integrated Services Digital Network (ISDN).
Systems wherein microprocessors operate in association with and require access to external devices are well known in the art. Such external devices may include one or more registers which the microprocessor must read data from or write data into. Such internal devices may also be the source of error messages or interrupt messages. In order for the overall system to function properly, the microprocessor must therefore be able to communicate with the external device to access registers and receive error and interrupt messages from the external devices.
Register access, error, and interrupt messages generally require multiple-bit messages to be conveyed between the microprocessor and the external device. In most applications and especially where integrated circuits are employed, it is not economically prudent to convey the bits of these messages between the microprocessor and the external device in parallel. To do so would result in an inordinately high cost due to such factors as the required multiple wire interconnection and the large number of required integrated circuit device terminal pins. With respect to this last mentioned factor, it is well known in the integrated circuit industry that the cost of producing an integrated circuit device increases as the number of required device terminal pins increases. Also, the number of device terminal pins is also related to the number of different functions that a device is to provide. Hence, it is advantageous to maintain the number of device terminal pins to a minimum while still affording a device with its complete and desired functionality.
In view of the foregoing, in multi-feature integrated circuit devices which are to be external to and or utilized in association with a microprocessor, a serial bus is often employed to provide multiple-bit messages to be sent from and received by the external device with respect to the microprocessor. This results in just two terminal pins and bus conductors being required, one for outgoing messages and one for incoming messages.
Unfortunately, in the prior art, communication system architectures and protocols have not made communication over serial buses between microprocessors and external devices very efficient. Such systems generally require a full, eight-bit byte to be conveyed just to define a particular operation such as a register access operation or to define a message as an interrupt or error messenger. Further, such systems have generally not provided multi-byte data access.
The present invention overcomes these disadvantages in the use of a serial bus between a microprocessor and an external device by requiring only a portion of an eight-bit byte to define an operation such as a register access operation or a message as an error or interrupt message. In addition, the system of the present invention utilizes a single message generator in the external device to generate read response, error, and interrupt messages. All of these types of messages are similarly formatted and placed onto the serial bus within the same predetermined channel. As a result, fast and efficient message transfer is obtained with a minimum amount of hardware.